The present invention generally relates to erasable programmable nonvolatile memories and, more particularly, to a writing circuit for such memories capable of writing data for a plurality of addresses as a batch to a plurality of memory cells in parallel.
For nonvolatile memories, especially of flash memory type, it is necessary to finely control the memory's threshold values for write/erase operations with a view to maintaining the reliability during long-time use. It is also necessary to reduce damage to the memory cells by minimizing write pulses.
Meanwhile, in order to meet longer write/erase times due to increased capacities of memories, particularly for write operation, a technique of writing to a plurality of memory cells in one batch is adopted.
In a known batch writing technique, parallel input/output is executed for a plurality of memory cells, and the processing is done with the plurality of cells taken as one address. In this technique, the writing to the plurality of cells of the address is completed at a time when the writing of the slowest bit, which needs the largest number of write pulses, ends.
However, in this parallel write operation, when the number of pulses necessary for write operation differs from bit to bit, i.e., from memory cell to memory cell, the following problem would be involved in writing operation in which a plurality of memory cells are taken as one address.
That is, because the parallel processing is done for a plurality of bits, there is a possibility that write pulses more than necessary are applied to memory cells corresponding to bits other than the slowest bit. That is, excessive writing may be done on the bits other than the slowest bit. This excessive writing is quite disadvantageous in view of the aforementioned threshold-value control of write cells and the retention of reliability.
Thus, in order to mend this disadvantage, verify process is performed for each bit even in the parallel processing of a plurality of bits, by which the application of additional pulses is controlled. The following techniques (1) and (2) are available as a technique for controlling the application of additional pulses:
(1) Based on verify data, write data is processed and reset so that only bits that need additional pulses are left, and additional write operation is continued until the writing of all the bits under parallel processing is completed. This processing is performed by a processing unit, such as a microcomputer built in the nonvolatile memory or installed outside of it;
(2) Data is reset without the aid of the processing unit and additional write operation is continued. One example of this technique is disclosed in Japanese Patent Laid-Open Publication HEI 5-290585. In this example disclosed, parallel processing of a plurality of bits is restricted to progression by steps of one address, so that simultaneous processing of a plurality of bits and of a plurality of addresses responsive to recent days' large capacities could not be performed. As a result, there is a problem that, in proportion to the increase in the memory size, the write time as a whole is prolonged.
As shown in the prior art example, as the write operation of a plurality of bits is performed by steps of one address, namely, address by address, the write time of the whole memory is increased especially in the case of a large-capacity memory, which may incur an inconvenience in use.
Also, with the write operation by the address, it is more likely that the total number of write pulses involved in writing to the full memory becomes larger, as compared with the batch writing of a plurality of addresses.
As a result of this, memory cells other than those that have been selected for application of write pulses would undergo write disturb for a long time, leading to an increase in variations of the write-cell threshold value. Moreover, increased stress on the memory cells may adversely affect the reliability of the memory cells.
Particularly in the case of flash memory type nonvolatile memories, memory cells other than a write memory cell that is being written are fed with a weak write bias, resulting in write disturb. One example of this is explained with reference to FIG. 6. In FIG. 6, if a cell 5 is written, a voltage VPP (V) is applied to the cell drain as a write bias, while a voltage of 0 V is applied to the cell gate. In this case, for a cell 2 and a cell 8 on the same word line (WL1) as the cell 5, a voltage of 1/2 VPP (V) is applied to the cell drain, while a voltage of 0 V is applied to the cell gate, so that a weak write bias of potential difference 1/2 VPP is applied. At this point, if the cell 2 and the cell 8 have been in an erased state, the cell 2 and the cell 8 change to a written state, thus resulting in deteriorated reliability with respect to the state retention of the cells 2, 8.
Likewise, with respect to a cell 4 and a cell 6 on the same bit line (BL1) as the cell 5, a voltage of VPP is applied to the cell drain while a voltage of 1/2 VPP is applied to the cell gate, so that a weak write bias with potential difference 1/2 VPP is applied. As a result, the cells 4, 6 are adversely affected like the cells 2, 8. This adverse effect is the write disturb. The total amount of this disturb is given by the product of the magnitude of the bias that makes disturb (aforesaid 1/2 VPP) and the time during which the cells undergo the disturb. The time during which the cells undergo the disturb is the time during which write pulses are fed.
Therefore, write operation on the 1-address basis requiring a longer total write pulse time would involve more write disturb than write operation in batches of a plurality of addresses requiring a shorter total write pulse time.